A DRAM cell is provided to store a bit of information. Each memory cell typically consists of a storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. The formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits.
With the advance of the integrated circuits, the requirement of the capacitance of the capacitor is continuously increasing. In order to achieve high packing density of a wafer, the memory cells must be scaled down in size to the sub-micrometer range. As the memory cells decrease in size, the area of the capacitors also decrease, resulting in a reduction of cell capacitance. For very small memory cells, capacitors become very difficult to use reliably. Specifically, as the size of the capacitor decreases, the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to .alpha. particle interference. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often.
Prior art approaches for overcoming these problems have resulted in the development of a memory cell with a hemispherical grained silicon (HSG-silicon) storage node. (See for example "A Capacitor-Over-Bit-Line Cell with a Hemispherical Grain Storage Node For 64 Mb Drams", IEDM Tech Dig., Dec. 1990, pp 655-658.) The HSG-silicon is deposited by a low pressure chemical vapor deposition method. Deposition is performed at a temperature of 550 centigrade degrees with He diluted. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node. The HSG-silicon storage node can be fabricated by the addition of two process steps, i.e. HSG-silicon deposition and an etch back. Further, in U.S. Pat. No. 5,104,821, Choi teaches a method of forming a capacitor for a DRAM cell. However, the capacitance cannot meet the requirement of future high density DRAM application.
In addition, the present invention uses high etching selectivity among BPSG (boro-phospho silicate glass), PSG (phospho silicate glass), BSG(boro silicate glass), NSG (undoped silicon glass) to form a stair-like resulting structure. The etching rates of the aforesaid materials under HF vapor are proposed by H. Watanabe, et al., "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256 Mb DRAMs", 1992, IEEE, 92-259.